Prof. Dr.-Ing. Alberto Garcia-Ortiz

ORCID iD orcid.org/0000-0002-6461-3864

Chair for Integrated Digital Systems, ITEM
University of Bremen (NW1)
Otto-Hahn Allee 1
28359 Bremen Germany

Tel. +49 (0) 421 218 62533
Fax. +49 (0) 421 218 9862533
Office: NW1 W3120
agarcia (at) item.uni-bremen.de

Short CV (German)

1992-1997

 

Studium der Nachrichtentechnik, Schwerpunkt Elektrotechnik an der Polytechnischen Universität Valencia

1997-1999

NewLogic Consulting and Technology GmbH (Austria)

1999-2003

Wissenschaftlicher Mitarbeiter und Wissenschaftlicher Assistent an der TU Darmstadt

2003

 Promotion zum Dr.-Ing.

2003-2005

IBM Deutschland Developmentand Research, Böblingen (Stuttgart)

2005-2010

Anafocus, Seville (Spain)

seit 2010

Professor für Integrierte Digitale Systeme an der Universität Bremen

Professional Activities

2019:Program co-chair of the International Conference on Modern Circuits and Systems Technologies.
2018:Workshop co-chair of the International Conference on Distributed Computing in Sensor Systems.
2017:Program co-chair of the International Symposium on Power and Timing Modelling, Optimization and Simulation.
2016:General Chair of the International Workshop on CMOS Variability.
2016:General Chair of the International Symposium on Power and Timing Modeling, Optimization and Simulation.
2015:General Chair of the International Symposium on Reconfigurable and Communication Centric Design.
2013:Program Co-Chair of the International Workshop on Reconfigurable and Communication Centric Design.
2012:Co-chair of the EOS Topical Meeting on Silicon Photonics, Aberdeen.
Since 2011: Reviewer for the DFG Deutsche Forschungsgemeinschaft.
2010: Reviewer for the German-Israeli Foundation for Scientific Research and Development (GIF)
2006: Reviewer for the Austrian National Research Society (Österreichische Forschungsförderungsgesellschaft)
Since 2005: Editor on board and reviewer of the Journal of Low Power Electronics from American Scientific Publishers.

Research topics

My current research topics concentrate on the following areas areas:

  1. Low-Power Design: Low-power coding, stochastic computing, dedicated hardware accelerators, etc.
  2. New Technologies: Vision-Systems-on-Chip, 3D-integration, reversible circuits, nanophotonic technologies, etc.
  3. Multiprocessor Architectures: Networks-on-Chip, Hardware Operative-Systems, massive parallel architectures, etc.
  4. Wireless Sensor Networks Data compression, task scheduling, etc.

Lectures

As full professor for the chair of Integrated Digital Systems, my teaching responsibilities cover a wide range lectures. I strongly committed to teaching; my goal is to provide a solid education that combines a deep theoretical background with the practical skills demanded by companies today. Currently, I am holding the following lectures and labs:
  • Fundamentals in Digital Technology
  • Laboratory Fundamentals in Digital Technology
  • Design Methodologies with Hardware Description Languages
  • Digital Technology
  • Advance Digital System Design
  • Architectures and Design Methodologies of Integrated Digital Systems
  • System-on-Chip: Architectures and Design Methods
  • Laboratory Design of Digital Systems

Publications

Patents

  1. Circuits and methods allowing for pixel array exposure pattern control. Pat. US8063350 B2. E. John McGarry, Rafael Dominguez-Castro, and Alberto Garcia. U.S. Classification 250/208.1, 257/258, 348/302, 348/308, 348/294, 257/292; International Classification H01L31/00, H01L27/00, H04N5/335, H04N3/14; Cooperative Classification H04N5/2353, H04N5/3535, H04N5/35554, H04N5/378; European Classification H04N5/355B1A, H04N5/353B, H04N5/235E, H04N5/378. Nov. 22, 2011.
  2. Estimating static power consumption of integrated circuits using logic gate templates. Pat. US7681153 B2. Cedric Lichtenau, Alberto Garcia-Ortiz, and Norman J. Rohrer. U.S. Classification 716/136, 716/103; International Classification G06F17/50; Cooperative Classification G01R31/2837; European Classification G01R31/28F4B. Mar. 16, 2010
  3. Method and apparatus for on-the-fly minimum power state transition. Pat. US7757137 B2. Alberto Garcia Ortiz, Cedric Lichtenau, and Norman J. Rohrer. U.S. Classification 714/726, 714/729, 714/727, 714/708, 714/15, 714/30, 714/34; International Classification G01R31/28; Cooperative Classification G01R31/318541, G01R31/318575; European Classification G01R31/3185S2. July 13, 2010.

Books

    Publications in journals

      Publications in conferences