Dr.-Ing. Amir Najafi

Scientific Assistant/Postdoc Researcher

Chair for Integrated Digital Systems, ITEM
University of Bremen (NW1)
Otto-Hahn Allee 1
28359 Bremen Germany

Tel. +49 (0) 421 218 62517
Fax. +49 (0) 421 218 9862517
Office: NW1 W3140
amir.najafi (at) item.uni-bremen.de

Research Topics

My current research topics concentrate on the following areas areas:

  • Approximate Processing
    Full-system approximation - Approximate Networks-on-Chip - Approximation for machine leaning applications

Teaching

Project-, Bachelor- and Masterthesis

  • I offer Master thesis/Project in the field of Approximate Communication, . For more information, please contact me.
.

Project

I am currently involved in the follwing research projects:
  • 3D Interconnection:
    Analysis of 3D monolithic NoCs for nanometric technologies.
  • Hybrid NoCs:
    Source-synchronous data transmission for circuit-switched NoCs.
  • Machine Learning Robustness:
    Effect of approximation/quantization and Signle event transient Error (SET) on classification accuracy of different neural networks.

Publications

  1. Yarib Nevarez, Andreas Beering, Amir Najafi, Ardalan Najafi, Wanli Yu, Yizhi Chen, Karl-Ludwig Krieger, Alberto Garcia-Ortiz "CNN Sensor Analytics With Hybrid-Float6 Quantization on Low-Power Embedded FPGAs"  IEEE Access, 2023 DOI: 10.1109/ACCESS.2023.3235866 ©IEEE
  2. Amir Najafi, Ardalan Najafi, Yarib Nevarez, Alberto Garcia-Ortiz. "Learning-Based On-Chip Parallel Interconnect Delay Estimation"  11th International Conference on Modern Circuits and Systems Technologies (MOCAST) 2022 DOI: 10.1109/MOCAST54814.2022.9837716 ©IEEE
    Preprint
  3. Amir Najafi, Ardalan Najafi, Alberto García-Ortiz. "Stochastic Wave-Pipelined On-Chip Interconnect"  IEEE Transactions on Circuits and Systems II: Express Briefs DOI: 10.1109/TCSII.2020.2984194 ©IEEE
    Preprint
  4. Amir Najafi and Lennart Bamberg and Alberto García-Ortiz. "Misalignment-aware energy modeling of narrow buses for data encoding schemes"  Integration, the VLSI Journal, 2020, in press DOI: ©ELSEVIER
    Preprint
  5. Amir Najafi, Lennart Bamberg, Ardalan Najafi, Alberto García-Ortiz. "Integer-Value Encoding for Approximate On-chip Communication"  IEEE Access, 2019 DOI: 10.1109/ACCESS.2019.2959446 ©IEEE
    Preprint
  6. Amir Najafi, Lennart Bamberg, Guillermo Payá Vayá and Alberto Garcia-Oritz "A Coding Approach to Improve the Energy Efficiency of Approximate NoCs"  14th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), July 01-03 2019, York (United Kingdom). ©IEEE
    Preprint
  7. Lennart Bamberg, Amir Najafi and Alberto Garcia-Ortiz. "Edge Effect aware Low-Power Crosstalk Avoidance Technique for 3D Integration" 
    Integration, the VLSI Journal, 2018, in press, ©ELSEVIER
    DOI: 10.1016/j.vlsi.2018.03.008 PDF
  8. Lennart Bamberg, Amir Najafi and Alberto Garcia-Ortiz. "Edge Effects on the TSV Array Capacitances and their Performance Influence" 
    Integration, the VLSI Journal, vol. 61, pp. 1-10, March 2018, ©ELSEVIER
    DOI: 10.1016/j.vlsi.2017.10.003 PDF
  9. Amir Najafi, Lennart Bamberg and Alberto Garcia-Ortiz. "Misalignment-Aware Delay Modeling of Narrow On-chip Interconnects Considering Variability" 
    7th International Conference on Modern Circuits and Systems Technologies (MOCAST), May 7-9 2018, Thessaloniki (Greece), ©IEEE
    DOI: 10.1109/MOCAST.2018.8376593
  10. Lennart Bamberg, Amir Najafi  and Alberto Garcia-Ortiz. "Edge Effect Aware Crosstalk Avoidance Technique for 3D Integration"  27th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS), Sep. 25-27 2017, Thessaloniki (Greece) ©IEEE
    (Best Paper Award - Soon published in IEEE Xplore )
  11. Alberto Garcia-Ortiz, Lennart Bamberg and Amir Najafi. "Low-Power Coding: Trends and New Challenges"  Journal of Low Power Electronics, Volume 13, Number 3, September 2017, pp. 356-370(15), DOI: 10.1166/jolpe.2017.1507 ©American Scientific Publishers
  12. Amir Najafi, Lennart Bamberg, Ardalan Najafi and Alberto Garcia-Ortiz. "Energy Modeling of Coupled Interconnects including Misalignment Effects"  Int. Symposium on Power and Timing Modeling, Optimization and Simulation, Sep. 21-16 2016, Bremen (Germany), DOI: 10.1109/PATMOS.2016.7833697 ©IEEE