Ardalan Najafi

Scientific Assistant/Ph.D. Candidate

Chair for Integrated Digital Systems, ITEM
University of Bremen (NW1)
Otto-Hahn Allee 1
28359 Bremen Germany

Tel. +49 (0) 421 218 62518
Fax. +49 (0) 421 218 9862518
Office: NW1 W3140
ardalan (at) item.uni-bremen.de

Research Topics

My current research topics concentrate on the following areas:

  • Inexact and Error Tolerant circuits and systems
    Approximate circuits
  • Ultra-low-power Arithmetic Units
    Sub-threshold desing
  • Stochastic Computing
    Voltage/frequency over-scaled circuits

Lectures and Teaching

Bachelors

  • Design Methodologies with Hardware Description Languages

Masters

  • Digital Technology
  • Advanced Digital System Design

Project, Bachelor and Master Theses

  • I offer several theses in the field of Digital Arithmetic Circuits, Circuit design with VHDL, and Stochastic Computing. The theses should be written in English. For more information, please contact me personally.

Project

I am currently involved in the follwing research projects:

  • Ultra-low-power computing units combining stochastic and sub-threshold approaches (Ph.D. research project)
  • Quantifizierung des Trade-Offs zwischen Energie und Berechnungsgenauigkeit in computer vision Prozessorarchitekturen erweitert mit stochastischen Berechnungsmechanismen
    • - The project is carried out in cooperation with Institute of Microelectronic Systems (IMS) at the Leibniz Universität Hannover, and funded by the German Research Society ("Deutsche Forschungs Gesellschaft (DFG)")

Latest Publication

ORCID iD orcid.org/0000-0002-6529-4084
Google Scholar

  1. Amir Najafi, Ardalan Najafi, Alberto García-Ortiz. "Stochastic Wave-Pipelined On-Chip Interconnect"  IEEE Transactions on Circuits and Systems II: Express Briefs DOI: 10.1109/TCSII.2020.2984194 ©IEEE
    Preprint
  2. Wanli Yu, Ardalan Najafi, Yarib Nevarez, Yanqiue Huang, and Alberto Garcia-Ortiz. "TAAC: Task Allocation Meets Approximate Computing for Internet of Things"  IEEE International Symposium on Circuit and Systems (ISCAS), May 17-20 2020, Seville (Spain), ©IEEE
  3. Amir Najafi, Lennart Bamberg, Ardalan Najafi, Alberto García-Ortiz. "Integer-Value Encoding for Approximate On-chip Communication"  IEEE Access, 2019 DOI: 10.1109/ACCESS.2019.2959446 ©IEEE
    Preprint
  4. Ardalan Najafi, Alberto García-Ortiz "Stochastic Mixed-PR: A Stochastically-Tunable Low-Error Adder"  IEEE Transactions on Circuits and Systems II, 2019 DOI: 10.1109/TCSII.2019.2953617 ©IEEE
    Preprint
  5. Mingjie Hao, Ardalan Najafi, Alberto García-Ortiz, Ludwig Karsthof, Steffen Paul, Jochen Rust. "Reliability of an Industrial Wireless Communication System using Approximate Units" In Power and Timing Modeling, Optimization and Simulation (PATMOS), 2019 29th International Workshop on. IEEE, 2019.
  6. M. Weißbrich, L. Gerlach, H. Blume, A. Najafi, A. García-Ortiz, G. Payá-Vayá "FLINT+: A runtime-configurable emulation-based stochastic timing analysis framework"  Integration, the VLSI Journal, 2019, in press DOI: 10.1016/j.vlsi.2019.01.002 ©ELSEVIER
    Preprint
  7. Ardalan Najafi, Moritz Weißbrich, Guillermo Payá Vayá, and Alberto Garcia-Ortiz. "Coherent Design of Hybrid Approximate Adders: Unified Design Framework and Metrics." IEEE Journal on Emerging and Selected Topics in Circuits and Systems, 2018. DOI: 10.1109/jetcas.2018.2833284 ©IEEE
    Preprint
  8. Ayad Dalloo*, Ardalan Najafi*, Alberto Garcia-Ortiz*. "Systematic Design of an Approximate Adder: The Optimized Lower-part Constant-Or Adder", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, pp. 1-5, 2018. DOI: 10.1109/TVLSI.2018.2822278 ©IEEE
    Preprint
  9. Moritz Weißbrich, Ardalan Najafi, Alberto Garcia-Ortiz, and Guillermo Paya-Vaya. "ATE-Accuracy Trade-Offs for Approximate Adders and Multipliers in Pipelined Processor Datapaths." 2018 Third Workshop on Approximate Computing (AxC18, www.lirmm.fr/axc18).
  10. Ardalan Najafi, Moritz Weißbrich, Guillermo Payá Vayá, and Alberto Garcia-Ortiz. "A Fair Comparison of Adders in Stochastic Regime." In Power and Timing Modeling, Optimization and Simulation (PATMOS), 2017 27th International Workshop on. IEEE, 2017.
  11. Moritz Weißbrich, Guillermo Paya-Vaya, Holger Blume, Ardalan Najafi, and Alberto Garcia-Ortiz. "FLINT+: A Runtime-Configurable Emulation-Based Stochastic Timing Analysis Framework." In Power and Timing Modeling, Optimization and Simulation (PATMOS), 2017 27th International Workshop on. IEEE, 2017.
  12. Amir Najafi, Lennart Bamberg, Ardalan Najafi, and Alberto Garcia-Ortiz. "Energy modeling of coupled interconnects including intrinsic misalignment effects." In Power and Timing Modeling, Optimization and Simulation (PATMOS), 2016 26th International Workshop on, pp. 262-267. IEEE, 2016.
* All the authors contributed equally to the publication.